Please login/register to apply for this job.
4 Aug 2022

Full-Time Design Verification Engineer X 5

MyNiceJob – Posted by mynicejob San Jose, CA Toronto, Canada

Job Description

 Mid-senior
 5 Years
 Bachelor’s degree
 Information Technology
 Information Technology and Services
open
 5
 Yes
 Only US citizens and Greencard holders

 

You will be part of the ASIC Verification Team, creating and bringing to market GEO’s next generation automotive camera video/vision processors.  Located in our San Jose or Toronto office, you will have the following responsibilities:

  • Develop test strategies to verify next generation camera processors
  • Develop and review block and chip level verification environments and test plans
  • Work closely with design engineers to develop test benches and test plans to meet coverage goals
  • Participate in selecting best in class 3rd party protocol verification IP
  • Help enhance the overall DV methodology by analyzing 3rd party verification tools
  • Debug failures in simulation and collaborate with designers in identifying root-cause issues
  • Develop a tests that will help achieve functional safety goals that meet ISO26262 compliance
  • Work with the systems and software teams on emulation platforms
  • Participate in the bring-up and debug of the device prototype
  • Provide support to the Product Engineering team to meet all validation and qualification goals for the product

MINIMUM QUALIFICATIONS

  • BSEE/BSCE/BSCS
  • 5 years of industry experience in design verification
  • Experience with test planning, test bench architecture and assertions
  • Constrained random verification experience with SystemVerilog using UVM
  • Coverage driven verification (code/functional/assertion coverage)
  • Strong programming skills in C/C++ and scripting experience with Python/Tcl/Perl

MUST HAVE

BSEE/BSCE/BSCS

5 years of industry experience in design verification

Experience with test planning, test bench architecture and assertions

Constrained random verification experience with SystemVerilog using UVM

Coverage driven verification (code/functional/assertion coverage)

Strong programming skills in C/C++ and scripting experience with Python/Tcl/Perl

See also ACIS Design Engineer also 5 positions

Job Categories: Information Technology. Job Types: Full-Time. Job Tags: BSEE, Design Verification Engineer, and Python.

Endless.

Apply for this Job